The present invention relates to a method of diagnosing an integrated logic circuit, especially a logic circuit implemented in the form of a large scale integrated circuit, and in particular to a method of diagnosing a logic circuit by using contactless probing techniques.
As a method of diagnosing a logic circuit, there is a method using a fault dictionary as described in "Fault Diagnosis of Digital Systems", H.Y. Chang et al., 1970, pp. 126 to 140, John Wiley & Sons, Inc., for example.
When abnormality is found in a signal at a certain point of a logical circuit to be diagnosed, it is possible to know which point of the circuit causes that abnormality by referring to a list made beforehand by means of simulation or the like. This list is a fault dictionary.
However, the time required for the fault simulation for making this fault dictionary increases in proportion to the number of elements to the 2nd or 3rd power. Thus, as the logic circuit is implemented in a large scale integrated circuit and the scale of the logic circuit is increased, therefore, the simulation for the fault diagnosis needs an extremely long time. Further, the fault dictionary itself needs a large memory capacity.
As described above, the fault diagnosis of an integrated logic circuit has now become extremely difficult as the number of integrated components is increased.
As one potent method for solving the above described problem, contactless probing techniques have been developed. In accordance with these techniques, the signal potential within an element is measured by using an electron beam or a laser beam.
One of the above described techniques is
described in IEEE, "Design & Test of Computers", Vol. 2, No. 5, Oct. 1985, pp. 74 to 82.
In accordance with the technique described in "Design & Test of Computers", the logic operation of the measured integrated circuit is held at a certain time point, and the chip surface of the integrated circuit at that time point is observed by using a stroboscopic scanning electron microscope (stroboscopic SEM).
The SEM image provides a wiring pattern image of the top layer depending upon the logic state of the integrated circuit at that time point. For example, a wiring pattern of logic "0" is bright and visible, and a 5 wiring pattern of logic "1" is dark and invisible. As a result, it is possible to obtain a wiring pattern image depending upon the logic state of the integrated circuit.
Subsequently, the above described pattern image actually obtained is compared with an expected wiring pattern image reproduced on the basis of the logic simulation and mask pattern data. The fault diagnosis can thus be effected.
As described above, the method using a fault dictionary has problems that the fault simulation needs an extremely long time as the logic circuit scale is increased and the fault dictionary itself needs a large memory capacity.
Further, the above described method using a conventional contactless testing equipment has a problem that faulty logic operation relating to timing such as the delay time or hazards cannot be detected because the logic operation must be held at a certain time point for the detection. Further, both the time required for the logic simulation and the time required for reproducing the expected wiring pattern image become extremely long as the scale of the integrated circuit is increased. This results in a problem of very long fault diagnosis time.